Synflow is an open source technology built by engineers for makers who want to create purpose built systems using FPGAs. It features a light weight, smart Software Development Kit (SDK) and a C-based language tailored to ease the development on FPGAs. The Synflow SDK generates vendor neutral code that can be used with any FPGA on the market.
Cx (C-extended) is an open language we created to develop applications and IP cores on FPGAs (or ASICs). We view Cx as what Verilog should have been: a language with syntax similar to the C programming language which is already widely used in engineering software development. Cx is designed for ease of development and scaling.
The Synflow SDK is a set of Eclipse plugins coded in Java. The SDK analyses your Cx code as you develop your system and it provides live feedback. For example, it automatically generates a network view or an FSM view that display how your code will be executed on an FPGA. The SDK is also capable of advanced code completion, refactoring, and code analysis.
We believe flexibility and scalability guarantee top performance and easy integration in all processes. That is why our compiler compiles Cx code into Verilog (or VHDL) according to strict coding rules provided by FPGA vendors. The generated code is therefore synthesiser friendly and offer better performance than hand written code. It is also readable so you can actually understand the generated Verilog and eventually further optimize your Cx code.
Cx is a modern language that required a modern simulator so we created one. Synflow Simulator (that is part of the SDK) allows the local execution of a core or a system 16 times (or more) faster than using traditional Verilog simulator. It is cycle accurate and bit accurate so you won't have any surprise when the time comes to test your system on an actual FPGA. The simulator uses Rust, a systems programming language that runs blazingly fast, prevents segfaults, and guarantees thread safety.
The Cx language and Synflow SDK have been created by two core developers. It is the result of one decade of work done at the National Institute of technology in Rennes, France, and at Synflow SAS, Sophia Antipolis, France. It can also be seen as a professional variant of the Open RVC-CAL compiler.
Hardware and Software Developer
Designer, Sales Rep, maker, and founder at Synflow. He has worked on everything related to the FPGAs, including apps, cores, and specific Java classes. He has also managed the sales.