At Synflow we develop technologies under Open Source and Commercial Licenses. Those technologies are built by engineers for makers who want to create purpose built systems using FPGAs. Our core product, the Synflow IDE features a C-based language that ease the development on FPGAs, and a smart SDK that generates vendor neutral hardware code to be used with any FPGA on the market.
Cx (C-extended) is an open language we created to develop applications and IP cores on FPGAs (or ASICs). We view Cx as what Verilog should have been: a language with syntax similar to the C programming language which is already widely used in engineering software development. Cx is designed for ease of development and scaling.
The Synflow SDK is a set of Eclipse plugins coded in Java. The SDK analyses your Cx code as you develop your system and it provides live feedback. For example, it automatically generates a network view or an FSM view that display how your code will be executed on an FPGA. The SDK is also capable of advanced code completion, refactoring, and code analysis.
We believe flexibility and scalability guarantee top performance and easy integration in all processes. That is why our compiler compiles Cx code into Verilog (or VHDL) according to strict coding rules provided by FPGA vendors. The generated code is therefore synthesiser friendly and offer better performance than hand written code. It is also readable so you can actually understand the generated Verilog and eventually further optimize your Cx code.
Cx is a modern language that required a modern simulator so we created one. Synflow Simulator (that is part of the SDK) allows the local execution of a core or a system 16 times (or more) faster than using traditional Verilog simulator. It is cycle accurate and bit accurate so you won't have any surprise when the time comes to test your system on an actual FPGA. The simulator uses Rust, a systems programming language that runs blazingly fast, prevents segfaults, and guarantees thread safety.
The Cx language and Synflow SDK have been created by a team of software and FPGA developers. It is the result of one decade of work done at the National Institute of technology in France, and at Synflow SAS. It was developed in partnership with companies specialized in ASIC design and IP cores providers.
Our mission is to develop compeling alternatives to HLS tools and HDL languages that ease and speed up the design of IP cores and systems. As of today, our customers design their products 3x to 20 x faster, and we are proud of that. We don't create High Level synthesys (HLS) tools because we don't believe in C to RTL compilation. We think engineers need a better option to design their products.
Hardware and Software Developer
Team Leader, FPGA engineer, and founder at Synflow. He has worked on everything related to the FPGAs, including apps, cores, and specific Java classes.